This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits can be designed as memory. Due to transistor scaling in modern circuitry, geometric scaling of metal and via routing can increase back-end wire RC load (i.e., resistor-capacitor load), which can degrade SRAM operation speed (i.e., static random access memory operation speed). For instance, since transistor geometry is being scaled down, the metal geometry is also scaled down. As a result, resistance (R) of the metal geometry can become a significant issue with advanced nodes, so developing a bitline differential for a higher number of rows can be challenging. These challenging issues can adversely impact timing and precharging of large RC of the bitline. These challenging issues can impact cycle time and power.